5. Designing the thermal vias
For the using of single layer PCB ,since no thermal vias is being deposited therein ,thus any heat sinking must be accomplished on the top layer entirely. This will typically require to generate
as large a thermal pad land as allowable (refer to 4.2.3)as well as filling all unused area with copper tied to thermal pad land to achieve a better heat dissipation .
Theoretically , the heat conduction paths from the device through the thermal vias underneath the device into the copper plane on the bottom layer are the most efficient paths in the PCB structure for heat dissipating. As such, at least 2-layer PCB with vias (1S1P) is highly recommended for the QFN/DFN applications.
5.1: The size of the thermal via
Practically, the heat would be transferred effectively from the device to the bottom layer of the PCB with a more number of vias and larger vias on the same thermal pad size ,but ,that results in lower package stand-off and solder protrusion due to solder tends to wick down the vias during solder reflow process, thus adversely affecting the strength and reliability of the solder joints.
Accordingly, the following is recommended
Via Pitch: 0.8~1.2mm, and 1.0mm is preferably
Via Dia.: 0.3~0.33m, and 0.3mm is preferably
(B)via tenting method : A round-shape of solder mask with a diameter larger 0.1mm than the diameter of via ( i.e. Ø0.4~0.43mm) is placed over the thermal via on the top side of the PCB to prevent solder wicking into the via, as shown in Fig.17.
Practically, the presence of the round-shape solder mask on the top side of the PCB will hinder proper solder paste printing , thus results an uneven solder coverage .As such, voids is likely being formed underneath the device, therefore the thermal performance is adversely being affected
(C) via encroaching method : The solder mask of the bottom side of the PCB is removed to expose a small diameter of copper around each of the thermal vias. As shown in Fig.18. The exposed copper should be normally 0.1mm larger than the diameter of the thermal via in order to restrict the migration of the solder across the bottom plane of the PCB.
The encroached vias allow the solder to wick inside the vias to prevent the voids from being formed. However, it also results in lower stand-off of the package due to solder protruding from the bottom side of the PCB, thus adversely affecting the strength and reliability of the solder joints. This solder protrusion can be avoided by using lower volume of solder paste and reflow peak temperature of less 215°C.
Accordingly, the encroached via is recommended due to less void and better thermal performance while PCB cost not being increased
6. Designing the Screen Print
6.1: Stencil’s thickness & materials
The thickness of the stencil determines the amount of solder paste deposited onto the PCB land pattern. Due to the fine pitch and small leads geometry of QDF/DFN being used, care must be taken while printing the solder paste on to the PCB .
Too much solder paste will cause solder bridging between the thermal pad under device and the leads on the perimeter of the device, too little solder paste will result in insufficient solder joint and lower stand-off, thus adversely affecting the reliability of the products.
6.1.2: Suggested thickness
a.) lead pitch ≤ 0.5mm, Suggested 0.127mm (5mil);
b.) lead pitch ≥ 0.65mm, Suggested 0.150mm (6mil)
Since QFN/DFN are not the only component on the actual application PCB, the above suggested stencil thickness of QFN/DFN may be thinner than other. In such case, a step down stencil is recommended where most of the component has its typical stencil thickness, but the area for the QFN/DFN would be reduce to 5 or 6 mils depending on the QFN/DFN’s lead pitch respectively
6.1.3: The material/making of the stencils
Stencils are usually made of brass or stainless steel, however, stainless steel is more durable and preferable. A Laser-cut or etch , stainless steel is recommended with an electro-polished trapezoidal sidewalls to achieve a more consistent paste release.
6.2: Designing the aperture opening of the finger pad
The area ratio of the aperture opening is critical in order for printing to get good solder paste
release. This is typically accomplished by considering the following two ratio;
a.) Area Ratio = aperture Area/Wall Area = LW/2T(L+W)
b.) Aspect Ratio = aperture width/stencil thickness = W/T
where L and W are the aperture length & width, and T is stencil thickness .
For optimum solder paste release, we recommend:
a.) Area ratio >0.66
b.) Aspect ratio>1.5
Accordingly, It is recommended that the stencil aperture should be 1:1 to finger pad size as both
of the area and aspect ratio are easily achieved by this aperture.
Further, For those spacing with 0.2mm between finger pad and thermal pad , it may be necessary to reduce the stencil aperture length by 20% for avoiding solder bridge from occurring in therebetween.
6.3: Designing the aperture opening of the thermal pad
The large thermal pad being screened with excessive solder may result the device “floating”, thus causing a non-wetting between the QFN/DFN leads and PCB due to solder surface tension during reflow.
It’s, therefore, recommended that a segmented stencil openings should be used instead of one big opening for printing solder paste to the thermal pad.
Accordingly, For exposed pad size < 16mm², a slotted shape opening is recommended. As shown in Fig. 19.
As such, the stencil opening will be approximately 50% ~ 80% of the thermal pad area, This will typically result in proper solder coverage of the thermal pad with fewer voids and minimizes the occurrence of solder bridging in between the thermal pad and perimeter leads.
7. Processing SMT
Maintaining a web width between opening of 0.3mm minimum is more feasible for the stencil fabrication.
7.1: MSL: Moisture Sensitivity Level
7.1.1: The QFN/DFN is a plastic encapsulated package, the epoxy molding compound (EMC) used for encapsulating tends to absorb moisture from the environment.Usually, the moisture is vaporized instantaneously when temperature rises during reflow, thus the expansion of moisture results in interfacial separation, known as delamination. Moreover, the package bulges once the internal high-pressure vapor is suddenly released from the package, known as “popcorn” effect.
Moisture trapped in the package will induce the effect of popcorn or delamination, thus leads to the failure of the device. Consequently, the MSL rating of QFN/DFN should be recognized in advance prior to SMT.
7.1.2: MSL indicates the floor life of the component after the dry bag is opened.
Table 2 presents the MSL rating respectively as per JEDEC J-STD-020c.
|Floor Life (after the dry bag is opened)
Components , under the environment of ambient temperature less than 30°C and Relative Humidity less than 60%, must be mounted and reflow within the allowable period time (floor life) according to their MSL rating after the original dry bag is opened.
If the components had been exposed to ambient air for a time longer than the specified MSL rating after dry bag being opened, the components are required a pre-baking prior to SMT in order to avoid popcorning from occurring.
Table 3 depicts the recommended baking time by the different baking temperature and MSL rating respectively.
|a.) @ 125℃
|b.) @ 90℃
7.2: Typical SMT
7.2.1 Solder Paste Materials
The QFN/DFN package has essentially low stand-off height. Therefore, post reflow flux cleaning is difficult. Accordingly, a no-clean solder paste is preferred.
7.3: Reflow temperature profile
There are no special considerations necessary when reflowing for QFN/DFN components. Practically, Temperature profile is the most important control in the reflowing process. The actual profile parameters depend upon the solder paste and recommendations from the paste maker should be followed. Further, To maximize the self-alignment effect of the QFN/DFN, It’s recommended that the peak reflow temperature specified for the paste should not be exceeded.
Since the actual profile depends upon the solder paste being used and component density of the PCB, Generally, Amtek does not recommend a specific profile for QFN/DFN.
Instead, for standard eutecdic (Sn/Pb)solder, the profile ramp-up rate of 3 °C /sec or less for preheat, followed by a ramp to peak temperature of profile and finally cool down at a rate no greater than 6 °C /sec is recommended .
Further recommendations, refer to JEDEC/JPC Standard J-STD-20a
7.3.1 QFN/DFN the lead finish materials for QFN/DFN packages
In response to the requirements of today’s Lead(Pb)-free and green components, NiPdAu pre-plated surface finish has been introduced to be an alternative Pb-free solution.
In order to adopt more environmentally friendly materials, Pre-plated leadframe(PPF), wherein a Cu base metal plated with Nickel, followed by Palladium with a thin flushed of Gold, is now being widely used for the leaded package, e.g. QFN/DFN.
Components with NiPdAu pre-plated finishs can withstand much higher reflow temperature than the traditional Sn/Pb finished components. Practically, the reflow peak temperature of PPF finished components needs to be increased more higher than Sn/Pb finished components, besides that, the trends of soldering issue seem to be the same as Sn/Pb finished components.
7.4: The check of solder joints following the reflow process
Unlike traditional leaded packages, the solder joints of QFN/DFN are normally formed underneath the package, Thus, The conventional visual inspection of the solder joints is time consuming undoubtedly. Consequently, X-ray inspection is recommended for verifying any open or short circuit of solder joints after reflow process.
It should be noted that solder non-wetting or solder balling on the peripheral leads is observed frequently while oxidation of the bare Cu on the side of leads is formed under an uncontrolled stored environment. As shown in fig.21.
The solder non-wetting or solder balling phenomenon generally does not present a reliability issue. It ‘s acceptable normally if no further ball-loosing or bridging being found.
However, It’s possible that a good solder joint of fillets can be obtained if the solder paste contained flux with a superior removal of oxidation is used.
Unlike the traditional leaded package, QFN/DFN’s solder joints are not fully exposed outside, As such , rework QFN/DFN packages can be a big challenge due to their small size and thin thickness, Moreover, QFN/DFN will be mounted on a dense PCBs ,thus, the proximity of other component will further complicate the rework due to handling and heating issues..
7.5.1 PreBaking prior to rework
To prevent moisture from inducing popcorn and/or delamination, a prebake consisted
of 125°C for at least 4 hours is highly recommended to remove the residual moisture from PCB & QFN/DFN to avoid the aforementioned failures from occurring prior to rework.
7.5.2 Steps for SMD rework
Generally, QFN/DFN rework are an adaptation of the traditional SMD components while many rework process step ,such as, component removal, site redress, solder paste/flux application, alignment, component placement and reflow have been adopted by industry customarily. As such, further description is hereby omitted.
However, The below two Metcal’s rework solutions may be considered seriously.
(A) Hand soldering : please refer to the application notes of MX-5000 series for details.
(B) Semi automated : please refer to APR-5000’s product details.
Please visit to : http://www.metcal.com,
for more information.